Course Outcomes:
After completion of this course, students will be able to –
|
3MVL2-13.1 |
Understand the basic significance of testing which can help them to design a better yield in IC design |
|
3MVL2-13.2 |
Apply the BIST architectures and techniques for improving testability. |
|
3MVL2-13.3 |
Demonstrate the Memory Test Algorithms and Techniques |
|
3MVL2-13.4 |
Analyze the test generation algorithms and testable combinational logic circuit design |
|
3MVL2-13.5 |
Outline the design for testability methods for sequential circuits |
CO-PO/PSO Mapping Matrix
|
COs |
PO 1 |
PO 2 |
PO 3 |
PSO 1 |
PSO 2 |
|
3MVL2-13.1 |
3 |
1 |
3 |
3 |
1 |
|
3MVL2-13.2 |
3 |
1 |
3 |
3 |
1 |
|
3MVL2-13.3 |
3 |
1 |
3 |
3 |
1 |
|
3MVL2-13.4 |
3 |
1 |
3 |
3 |
2 |
|
3MVL2-13.5 |
3 |
1 |
3 |
3 |
2 |
|
3MVL2-13 |
3 |
1 |
2 |
3 |
2 |
