Course Outcomes:
After completion of this course, students will be able to –
|
2MVL1-01.1
|
Comprehend the VLSI verification techniques. |
|
2MVL1-01.2
|
Define classes and create objects. |
|
2MVL1-01.3
|
Develop design using system Verilog. |
|
2MVL1-01.4
|
Make Verification environment using System Verilog. |
|
2MVL1-01.5
|
Create the UVM Verification environment and reusable verification environment |
CO-PO/PSO Mapping Matrix
|
COs |
PO 1 |
PO 2 |
PO 3 |
PSO 1 |
PSO 2 |
|
2MVL1-01.1 |
1 |
2 |
3 |
2 |
2 |
|
2MVL1-01.1 |
1 |
2 |
3 |
2 |
2 |
|
2MVL1-01.2 |
3 |
3 |
3 |
3 |
3 |
|
2MVL1-01.3 |
3 |
3 |
3 |
3 |
2 |
|
2MVL1-01.4 |
3 |
3 |
3 |
3 |
3 |
|
2MVL1-01.5 |
3 |
3 |
3 |
3 |
3 |
|
2MVL1-01 |
3 |
3 |
3 |
3 |
3 |
