Course Outcomes
After completion of this course, students will be able to –
|
1MVL1-02.1 |
Understand design metric and layout for various digital integrated circuits. |
|
1MVL1-02.2 |
Analyze the timing concepts in latch and flip-flops and interconnect and clocking issues. |
|
1MVL1-02.3 |
Design the CMOS inverter with optimized power, area and timing. |
|
1MVL1-02.4 |
Design static and dynamic digital CMOS circuits and CMOS memory arrays. |
CO-PO/PSO Mapping Matrix
|
COs |
PO 1 |
PO 2 |
PO 3 |
PSO 1 |
PSO 2 |
|
1MVL1-02.1 |
- |
2 |
3 |
3 |
1 |
|
1MVL1-02.2 |
- |
2 |
3 |
3 |
3 |
|
1MVL1-02.3 |
- |
2 |
3 |
3 |
3 |
|
1MVL1-02.4 |
- |
2 |
3 |
3 |
3 |
|
1MVL1-02 |
- |
2 |
3 |
3 |
3 |
