We are pleased to inform you that Swami Keshvanand Institute of Technology, Management & Gramothan, Jaipur is going to organize a National Workshop on “VLSI DESIGN FLOW USING CADENCE EDA TOOL (NWOCT-2016)” in Association with Entuple Technologies Pvt .Ltd., Indian Society for Technical Education (SKIT Student Chapter), The Institutions of Electronics and Telecommunication Engineers (SKIT Student Chapter) from 25th - 26th May, 2016.
Registration Deadline: May, 21, 2016 (registrations can be done online only through link provided above)
Intimation of Confirmation: May, 23, 2016
Registartion fee: 600 INR
The aim of this workshop is to provide hands-on Analog & Digitial (ASIC) VLSI Design Flow using the state-of-the-art Cadence EDA tools. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and RC Extraction of Layouts. The workshop includes practice sessions on the Cadence design and simulation tools (Encounter, RTL Compiler, Virtuoso, Spectre, Assura and Incisive).
First day will cover the full Analog flow using Virtuoso tool.
Second day will cover the Digital Design Flow using Encounter and RTL Compiler.